1. Field of the Invention
The present invention relates to a radio communication receiving device, and more particularly to a paging receiver that is activated by its detection of a preamble sent via a radio frequency carrier and thereby starts receiving digital code data that follows the preamble.
2. Description of the Prior Art
The radio paging receiver known internationally as a pager and in Japan as a "pocket bell" is one of the representative types of radio communication receiving device used to receive a digital signal code transmitted by radio. The present invention will be more readily understood if described in terms of an improvement to this type of pager (radio paging receiver) and such a pager will therefore now be described, with reference also to the prior art.
POCSAG is a coding protocol extensively used by pager systems for radio transmission of data. The data stream transmitted at a designated radio frequency from a transmitting base station to the individual pagers in accordance with this protocol is illustrated in FIG. 4.
As shown, first comes a preamble data section of alternating logical "1s" and "0s" forming a serial bit stream "1010 . . . 10" of at least 576 bits. This preamble data is followed by an arbitrary number of data batches 1, 2, 3, . . . . Each data batch starts with a specific synchronization code Sc which is followed by eight data frames numbered #0 to #7. In FIG. 4, frame #4 is shown in magnified detail, from which it can be seen that each such frame consists of a pair of code words 10 and 20, each 32 bits long. In accordance with the POCSAG format, bit allocation in each data frame is as follows.
The first bit (bit #1) in each of the code words is the address/message flag 11 (code word 10) and address/message flag 21 (code word 20). As shown, when the bit value of the address/message flag 11 is logical 0, the code word is address code word 10, and when the bit value of the address/message flag 21 is logical 1, the code word is message code word 20.
In the address code word 10 the 18-bit portion from bit #2 to bit #19 represents address data 12 for calling the pager having the same ID code, and bits #20 and #21 are for function data 13, which as 00, 01, 10 or 11 can designate four functions. The group of bits from #22 to #31 are BCH (Bose-Chaudhuri-Hocquenghem code) bits 14, and the final bit #32 is a parity bit.
When a 32-bit code word is a message code word, which is when the address/message flag bit #1 is logical 1, it consists of bits #2 to #21 representing message data 22, bits #22 to #32 as the BCH bits 23, and error-correction parity bits 24. The POCSAG message protocol does not limit the length of a message; when the message is long, code words of the next and subsequent data frames can also be used for the message. Message code words can also be stored in the data frames that follow the synchronization code Sc in each of the subsequent batches.
BCH bits 14 and 23 and parity bits 15 and 24 are used for correcting errors that occur in the data transmission process and for checking the results of such corrections. These are known techniques having no direct bearing on the present invention, and as such, further details thereof are omitted.
Each pager that conforms to the POCSAG transfer format is assigned at least one ID code, and especially nowadays may be provided with a plurality of such codes. FIG. 5 shows a typical pager according to the prior art. With reference to FIG. 5, ID codes are stored in an ID code memory 39 in the pager 30. These memories are usually programmable read-only-memories (PROMs) or, more recently, electrically-erasable PROMs (EEPROMs).
Pagers such as pager 30 are portable units which run off a battery power source 40. To enable the pager 30 to be used for extended periods, the POCSAG format incorporates battery-power saving or conservation features. More specifically, the pager 30 has a receiver 32 which uses an antenna 31 to detect, and then demodulates, radio signals of a specific frequency representing the logical values of each of the data bits transmitted in accordance with a frequency-modulation system, which is generally frequency-shift keying (FSK), and a wave-shaping circuit (also known as a digital detector) 33 that processes the output of the receiver 32 to enable it to be read as a digital signal, and battery power is supplied intermittently at time intervals .sub..DELTA. T to both the receiver 32 and wave-shaping circuit 33, or at least to the receiver 32. For this, in the case of the illustrated arrangement, a control circuit set is incorporated in a decoder 34, described below. Nowadays the tendency is to use a microcomputer 35 as a pager controller, in which case the microcomputer 35 may be one that can be switched into a low-power-consumption low clock mode when the supply of power to the receiver 32 or to the receiver 32 and wave-shaping circuit 33 is shut off.
FIG. 4 shows the receiver mode waveform. As shown, in the ON mode, the application of power from the battery to the receiver 32 (FIG. 5) is followed by a receiver stabilization period of from several milliseconds to over ten milliseconds. In the OFF mode the power supply is shut off and the receiver 32 assumes a resting state. Putting the receiver 32 into the ON mode basically means turning the pager on, and putting the pager into the OFF mode means turning it off.
The receiver 32 is switched on at periodic time intervals .sub..DELTA. T by a power supply control circuit provided with a time measuring function, located in the decoder 34. The receiver 32 mode switches to off if a preamble is not detected by the completion of the fixed time the ON mode is maintained, in which case the mode will be switched to on after the lapse of the prescribed time interval .sub..DELTA. T. Still with reference to FIG. 4, when a preamble is detected during the ON mode, the receiver 32 stays on and receives the synchronization data or synchronization code Sc that follows. The receiver 32 mode then switches to off until a predetermined data frame, for example frame #4, is received by the pager, and after the elapse of the time required to receive frame #4, the receiver 32 goes into the ON mode, and stays in that mode until the data in frame #4, and in subsequent data frames if it is a long message, has been received (and demodulated and decoded), after which it switches back off.
The POCSAG format has been planned so that the ID codes assigned to pagers enable each pager to determine which frames to read. Except for some special codes, any arbitrary number from decimal 0 to 2097152 (2.sup.21) can be utilized as a POCSAG-format code. However, FIG. 4 shows that only 18 bits are available for matching address data 12 and ID codes, as the three low-order bits are set aside for frame designation purposes. These three low-order bits can be used to represent binary 000 to binary 111 or decimal 0 to decimal 7. Thus, if a pager has been assigned a plurality of ID codes in which the three low-order digits thereof are all the same, each of the ID codes can be designated by the remaining high-order 18 digits and all of the ID codes can be assigned to the same frame. For example, if a pager is assigned a plurality of ID codes and frame #4 is designated, in assigning ID codes, numbers should be chosen from decimal 8 to 2097152 that when divided by 8 leave 4, such as 12, 20, 28, for example. Associating all ID codes with the same frame maximizes the effect of the above battery-saving function, as having to check a different frame for each ID code would increase the length of time the receiver is on, thereby draining the battery more quickly. While not directly prescribed by the POCSAG protocol, conventionally the numbers from decimal 0 through 7 are not used for ID codes, as using these numbers would make it possible for all the bits in an address code word 10 to be zeros, increasing the risk of errors.
Thus, it should be possible to expect good battery conservation with the POCSAG format. However, with respect to the frame set for each pager, for example frame #4, again with reference to FIG. 4, with bit #1 of the first code word being logical 0, meaning address code word 10 when the flag 11 is 0, the pager's decoder 34 compares the address data 12 bits #2 to #19 against all of the ID codes assigned to that pager. Also, if there are no ID codes that match the address data 12 the receiver 32 switches off, and switches back on after a prescribed time .sub..DELTA. T. If the address data 12 input to the decoder 34 matches any of the ID codes, the pager continues with the execution of the prescribed service function. It will be understood that "matching" as used herein refers not only to strict one-to-one identity, but also to broader types of correspondence, including look-up tables, and other comparison means.
The four types of function data 13 can each represent a designated function A, B, C, or D. For example, function data 00 could be used to designate function A to cause the pager speaker, or "beeper," 42 to emit two long beeps in succession, and, if required, to add a letter A at a prescribed position on a display 41 when message data is displayed on the display; function data 01 could correspond to a function B whereby the speaker 42 emits a short beep followed by a long beep and a letter B is displayed on the display 41; function data 10 could correspond to function C for two short beeps and a letter C displayed on the display 41; and function data 11 for function D might be used to cause the speaker 42 to emit four short beeps and display a letter D on the display 41. Functions A to D can be used for other purposes, such as control data for over-the-air remote programming to rewrite data in pagers in accordance with radio transmissions from a transmitting base station. However, as this has no direct relationship with the present invention, further description thereof is omitted.
When the decoder 34 confirms that there is a match between received address data and any of the ID codes assigned to the pager, the decoder 34 puts the microcomputer 35 into a high-clock mode (when the system has such a mode-switching capability), following which the second code word, message code word 20, is received and message data 22 is decoded, and BCH bit 23 and parity bit 24 are used to correct decoding errors and check the correction result, in accordance with a known process. Under the control of the microcomputer 35 the message data 22 thus checked is stored in a message memory, together with message data from subsequent frames if the message is a long one.
When the transfer of the message data has been completed, an alert means such as the speaker 42, a motor-driven vibrator 43 or a light-emitting diode (LED) 44 is activated to notify the pager user that a new message has been received. If the speaker 42 is used, for example, it might emit a preset beep pattern in accordance with function data 13. In some pagers the message is displayed simultaneously with the activation of the alert means, but usually the user will operate keys 38 to retrieve the message from memory and display it in alphanumeric form on the display 41, at a time chosen by the user. In the case of displays capable of displaying English characters, the display of a message is usually accompanied by the display at a specified position of one of the characters A to D corresponding to function data 13.
This pager is provided with all these alert means. Some pagers contain information to determine which means to use, stored for example in EEPROM 39, to enable the user to select which alert means is used. Some pagers may be provided only with the speaker 42 and the vibrator 43. Again, however, as these have no direct bearing on the present invention as described below, no further details thereof are included. The message memory area is usually capable of storing multiple messages. Messages can be sent to the display 41 in the order in which they arrive or in another order, such as the most recent message first. This too has no direct bearing on the present invention, so further details thereof are omitted.
When storage of the message data has been completed the receiver 32 is switched back into the OFF mode by the power control circuit in the decoder 34, and is periodically turned on at time intervals .sub..DELTA. T until the next preamble is detected.
Each of the ID codes assigned to a pager is reserved to carry out a designated function. Assuming that a pager has been assigned the codes 1, 2 and 3 (although nowadays a pager usually has a larger number of codes), the first code 1 can be assigned to just one pager. As such, when the transmitting base station transmits address data which matches that ID code, only the alert means of that pager will be activated to page the user. This ID code can therefore be termed an "individual call" code. In contrast, by assigning the second ID code, ID code 2, to a plurality of pagers furnished to a group of people having some type of relationship such as, for example, a group of employees in a company, all of those pagers can be activated by transmitting address data that matches ID code 2, making it a "group call" ID code. ID code 3 can be used as an individual call code, but when used to page the user can for example cause the speaker 42 to emit a special type of beep and a letter "U" to be displayed at a specific location on the display 41. Thus, ID code 3 can be used for "urgent calls." In recent years, particularly in the U.S., various paging pay services have been thought of. There is a mail drop service which can be used to periodically display stock prices, for example. As there are designated ID codes for each service, the demand now is for pagers in which four to six ID codes can be provided, and it seems clear that the future demand trend will be for more codes.
While in the foregoing description the decoder 34 decodes preambles, synchronization codes and code words in accordance with a digital pulse train that appears in the output of the wave-shaping circuit 33, in principle the detection and decoding circuits can be implemented as separate hardware components. Even with a limited number of input/output ports, as the speed and capacity of microcomputers continue to increase it will become possible for the functions of the decoder 34 to be taken over by the microcomputer 35. As mentioned, the integrated-circuit modules that form the decoders used in today's pagers incorporate power supply circuit sets that are provided with battery-saving time-measurement functions (i.e., timing control functions), and these can of course be implemented as separate, discrete circuits. Also, when control of the clock mode of the microcomputer 35 is not implemented, software processing can be used to utilize the microcomputer 35 itself as a circuit that controls the supply of power to each circuit in accordance with a prescribed timing. This can also apply to the decoder 36 and power supply limiting circuit 56 described in the embodiments of the invention.
Thus, in this type of radio paging receiver substantially all functions start with preamble detection. This is a measure of the importance of the preamble detection: obtaining the digital data concerned and the timing control for the battery-saving feature both depend on the accuracy of the detection. It is desirable to be able to perform high-sensitivity detection even when there is a poor carrier-to-noise (C/N) ratio. On the other hand, in view of the portable, battery-driven nature of radio paging receivers, the component circuits thereof should be as small and simple, and consume as little power, as possible.
From that standpoint there is still room for improvement in the above-described conventional preamble detection system. With the conventional system all of the analog base band signals appearing in the FM detection output of the receiver 32 are given a digital waveform by the wave-shaping circuit 33 and then applied to the decoder 34. However, to reduce the size of circuits most such decoders 34 are comprised of integrated-circuit modules which incorporate many functions. Therefore during the decoding process used to ascertain whether or not the train of digital signals being thus input is a preamble, power is also being supplied to operate all of the other function parts in the decoder, for example to the circuit that is used to perform parallel comparisons of incoming address data and each of the ID codes that are transferred from the EEPROM 39 to buffer memory by the microcomputer 35 when the power is turned on. At least up until the point at which a preamble is detected, this is a waste of electric power. Moreover, at the present stage this is less than perfect in terms also of performance; while digital processing may have been applied a high C/N ratio is not obtained, and in fact an internal noise problem may arise.